Field of the Invention
The present invention relates to a lateral double-diffused MOS field-effect transistor, also called LDMOS transistor for short. The device has a body zone provided in a semiconductor layer of a first conduction type. The body zone is of the second conduction type, opposite to the first conduction type. The device further has a highly doped source zone of the first conduction type located in the body zone, a highly doped drain terminal zone of the first conduction type provided in the semiconductor layer at a distance from the body zone, and a gate, with respect to which the body zone is self-aligned.
FIG. 5 shows a sectional illustration of a conventional LDMOS transistor with an n-channel (cf. T. Efland: Lateral DMOS Structure Development for Advanced Power Technologies in TI Technical Journal, March-April 1994, pp. 10-24). The conduction types specified are reversed in the case of a p-channel transistor. The transistor itself may be provided in an epitaxial layer applied on a semiconductor substrate. In this case, a highly doped buried layer may be located between the semiconductor substrate and the epitaxial layer. The buried layer, which may also be omitted if appropriate, may have the same conduction type as or opposite conduction type to the conduction type of the epitaxial layer. The semiconductor substrate preferably has the opposite conduction type to the conduction type of the epitaxial layer. An n-channel transistor will be taken as a basis below in order to simplify the illustration, although it goes without saying that the opposite conduction type and further variants are also possible. Silicon will be assumed to be the semiconductor material for the transistor. Instead of silicon, however, it is also possible to provide a different semiconductor material, such as, for example, silicon carbide, compound semiconductors, etc.
In the case of the conventional prior art LDMOS transistor of FIG. 5, an n-conducting epitaxial silicon layer 2 is provided on a p-conducting silicon substrate 1. An n+-conducting buried layer 3 is formed between the silicon substrate 1 and the epitaxial layer 2. The buried layer 3 may be formed by implantation and diffusion into the substrate 1 before deposition of the epitaxial layer 2 and outdiffusion after the deposition of the layer 2.
Situated in the epitaxial layer 2 are a p-conducting body zone 4 with a p+-conducting body terminal region 5 and an n+-conducting source zone 6, adjoined by a channel in the body zone 4 below polycrystalline silicon of gate 11. Moreover, an n-conducting buffer zone 7—doped more heavily than the epitaxial layer 2—with an n+-conducting drain terminal region 8 is provided at a distance from the body zone 4. The zone 7 and/or the terminal region 8 may also be omitted if appropriate. The gate 11 made of polycrystalline silicon or else some other suitable conductive material is situated on a thick insulating layer 9 made of field oxide, made of silicon dioxide for example, and on a thin insulating layer 10 made of gate oxide, such as, for example, likewise silicon dioxide.
The body terminal region 5 is provided with a body electrode B, while the source zone 6 is connected to a source electrode S. The body electrode and the source electrode are preferably interconnected to form an electrode S. The gate 11 is provided with a gate electrode G, while the drain terminal region 8 is connected to a drain electrode D.
The current path between the source electrode S and the drain electrode D is illustrated by a resistance or resistor R. The resistance of the resistor R depends on the voltage Vgs (Vgs=gate-source voltage) present at the gate 11. The channel region in the body zone 4 is diagrammatically represented by the corresponding part of the symbol of a MOS field-effect transistor.
In the case of the LDMOS of FIG. 5, the body zone 4 and the source zone 6 are implanted in a self-aligned manner via a hole in the polycrystalline silicon layer forming the gate 11, so that the length of the channel between the source zone 6 and the epitaxial layer 2 in the body zone 4 results from the differential outdiffusion of the source zone 6 and the body zone 4 after the implantation thereof. The drain comprises the region in the epitaxial layer 2 below the thick insulating layer 9, the buffer zone 7 and the drain terminal region 8. In this case, the buffer zone 7 and the drain terminal region 8 may be provided by different implantations of an n-conducting dopant, such as phosphorous or arsenic, for example. Boron is suitable as p-conducting dopant.
The concept of the LDMOS transistor illustrated in FIG. 5 has the essential advantage of a very short channel length in the region of the body zone 4 below the gate electrode G between the source zone 6 and the region of the drain that is formed by the epitaxial layer 2. Moreover, in this case the source zone 6 and also body zone 4 are self-aligned with respect to the gate 11, which has already been pointed out above. This self-alignment is associated with considerable advantages with regard to reduced parameter variations for, in particular, threshold voltage, on resistance, etc.
What is disadvantageous about the LDMOS transistor of FIG. 5, however, is its limited dielectric strength: the latter can be attributed to an unfavorable course of potential lines 12, which, at high voltages present at the drain electrode D, exhibit considerable bends especially in the region below the insulating layer 9, with the result that regions 13 wherein electrical breakdowns can readily occur are present there. Given economically acceptable on resistances of the LDMOS transistor, the dielectric strength thereof is thus limited to about 60 V (in this respect, cf. B. I. Baliga, Modern Power Devices, 1987, Krieger Publishing Company, pp. 81, 83 and 88, and S. Merchant et al., High Performance 13-65V rated LDMOS transistors in an advanced Smart Power Technology, ISPSD 1999).
In order to extend this limited dielectric strength, an alternative concept has already been conceived, namely the so-called RESURF (REduced SURface Field) LDMOS transistor, wherein the body zone—referred to here also as p-type well given the conduction type assumed above—extends over the entire area of the component. In this respect, reference is made to FIG. 6, which shows such a RESURF-LDMOS transistor with a p-conducting well 14 and an n-conducting RESURF zone 15. The RESURF zone 15 requires an additional implantation and forms a connection between source and drain. At high voltages present at the source electrode S and the drain electrode D, the RESURF zone 15 is completely depleted of charge carriers, which leads to a favorable course of the potential lines 12. The RESURF-LDMOS transistor of FIG. 6 is thus better suited to higher voltages than the LDMOS transistor of FIG. 5.
However, a considerable disadvantage of the RESURF concept of FIG. 6 resides in the fact that the channel length between the source zone 6 and the RESURF zone 15 below the polycrystalline silicon of the gate 11 in the well 14 is no longer self-aligned with the structure of the polycrystalline silicon, with the result that, with regard to small fluctuations which can readily occur due to the dictates of production, it has to be chosen to be longer than in the case of the LDMOS transistor of FIG. 5 (in this respect, also cf. T. Efland, supra). Problems on account of mask misalignments especially occur here.
It would be desirable, therefore, to combine the concept of an optimized on resistance on account of a self-aligned channel (cf. FIG. 5), with the concept of a high dielectric strength by virtue of an optimum course of the potential lines on account of the RESURF effect (cf. FIG. 6).
In order to achieve this aim, thought has already been given to using SOI (silicon on insulator) technology, which, on account of a depletion from the buried oxide, permits a self-aligned channel to be made compatible with a high dielectric strength. Moreover, it has already been proposed to provide, in bulk silicon, a RESURF transistor in the LDMOS concept with a gradated epitaxial layer in a well (cf. Merchant, supra).
FIG. 7 shows such a RESURF transistor: in this case, an n-conducting layer-like RESURF zone 15 is embedded in a p-conducting well 14′. In this case, the RESURF zone 15 is implanted areally over the active region of the LDMOS transistor before the field oxidation for the formation of the insulating layer 9. The p-conducting well 14′, which together with the RESURF zone 15 enables the RESURF effect, also covers the active region of the LDMOS transistor except for a small window below the drain, in order to enable a connection to the bottom layer. This leads to a “double” RESURF effect wherein the well 14′ is also depleted from below when a high drain voltage is present. In the case of this RESURF transistor, although the channel is self-aligned with respect to polysilicon, the p-conducting well 14′ is misaligned with respect to the drain (cf. misalignment δ in FIG. 7).
The two concepts, that is to say SOI technology and bulk silicon, are unconvincing, however, since they on the one hand require a relatively large outlay (SOI) and on the other hand adhere to the RESURF principle with the associated disadvantages (bulk).
One advantage resides in the fact that a deep body region does not reach the silicon surface, so that misalignments with respect to the drain result in lower parameter fluctuations than in the case of an arrangement wherein a p-conducting well has its maximum doping at the surface of the semiconductor layer. In the case of the RESURF effect with overlapping p- and n-conducting wells, the differential doping is very critical since a slight fluctuation in the doping of one of the wells greatly influences the depletion. With a deep body region, there is no such overlap in the drift path.